Silicon-based Integrated Photonics: Basic building blocks and the role of variations in device performance
Robert Geer, SUNY Polytechnic Institute
The success of Si as a platform for photonic devices and the associated availability of wafer-scale, ultra-high resolution lithography for Si CMOS has helped lead to the rapid advance of Si-based integrated photonics manufacturing over the past decade. This evolution is nearing the point of integration of Si-based photonics together with Si-CMOS for compact, high speed, high bandwidth, and cost-effective devices.
However, due to the sensitive nature of passive and active photonic devices, variations inherent in wafer-based fabrication processes can lead to unacceptable levels of performance variation both within a given die and across a given wafer. Fully understanding the role of variation in affecting integrated photonic device performance is an important component of scaling the design and manufacturing infrastructure for photonic integrated circuits.
This seminar will provide an introduction to Si-based integrated photonics and review the basic operation of Si-based integrated photonic devices. In addition, results will be presented regarding the impact of intra- and inter-die variation on integrated photonic device performance based on customized structures fabricated at SUNY Poly’s AIM Photonics Center.